As semiconductor devices become highly integrated, transistor size may be reduced, which may result in a variety of operational and structural problems. For instance, short channel effects may be increased, and punch-through characteristics between source and drain regions may deteriorate. In addition, the turn-on current of the transistor may be decreased, and transistor performance may be degraded.
To address some of these problems, fin field effect transistors (Fin-FETs) have been developed. A fin field effect transistor can include a gate electrode on an upper surface and sidewalls of a silicon fin that vertically protrudes from a semiconductor substrate. Source and drain regions may also be formed in the silicon fin on opposite sides of the gate electrode. Thus, a channel region may be formed at both sidewalls and at the upper surface of the silicon fin, such that the channel width of the transistor may be increased. In addition, the gate electrode can control the channel region at both sides, thereby improving device controllability. Furthermore, turn-on current may be increased due to the greater channel width, thereby improving both performance as well as punch-through characteristics between the source and drain.
However, problems may occur at corner portions of the channel region, i.e. where a sidewall portion and a top surface portion of the channel region meet.
FIG. 1 is a perspective view illustrating a conventional fin field effect transistor (Fin FET). FIG. 2 is a cross-sectional view of the Fin FET taken along line I–I′ of FIG. 1.
Referring to FIGS. 1 and 2, a silicon fin 2 vertically protrudes from a semiconductor substrate 1. A gate electrode 5 crosses over the silicon fin 2. In other words, the gate electrode 5 passes over both sidewalls and the upper surface of the silicon fin 2. A gate oxide layer 3 is formed between the gate electrode 5 and the silicon fin 2. Source/drain regions 6 are formed in the silicon fin 2 on both sides of the gate electrode 5.
The gate electrode 5 may include three parts: a first gate 4a at one sidewall of the silicon fin 2, a second gate 4b at the upper surface of the silicon fin 2, and a third gate 4c at another sidewall of the silicon fin 2. Accordingly, the channel region may include vertical channel portions formed at both sidewalls of the silicon fin 2 and a top channel portion formed at the upper surface of the silicon fin 2.
However, when a voltage is applied to the gate electrode 5 of a fin field effect transistor having the above-mentioned structure, the electric field may be concentrated on corner portions “A” of the fin 2, i.e. where the vertical channel portions meet the top channel portions. This may result in a “hump” in the subthreshold current. In other words, leakage current may occur at voltages lower than threshold voltage of the fin field effect transistor. As a result, characteristics of the fin field effect transistor may be degraded.